o  Full scene anti-allasing

o  Soft shadows and depth-of-field

o  FFTs and convolutions

o  Multimode windowing environment

The RISC-based IRIS-4D Series host CPU provides the graphics subsystem with the
description of 3D objects. This description takes the form of Graphics Library(tm)
commands and world coordinate vertex data; it describes the object's geometric
position, color, and surface normal vectors used for complex lighting calculations.  The
IRIS PowerVision graphics architecture performs transformations and other graphics
operations to calculate specific pixel values for each of the 1.3 million pixels on the
1280 x 1024 high-resolution display Visual data from the RISC host is processed by
four pipelined graphics.subsystems before being displayed on the screen:

o  geometry subsystem

o  scan conversion subsystem

o  raster subsystem

o  display subsystem

The geometry subsystem receives the 32-bit or 64-bit graphical data from the RISC-
based host and converts it to screen space data.  The scan conversion subsystem then
breaks down points, lines, polygons, and meshes into pixel data.  This pixel data is
sent to the raster subsystem, where the Z-buffer removes hidden surfaces.  The raster
subsystem also performs various blending and texturing functions on a pixel-by-pixel
basis as the pixels are written to the image bit-planes or frame buffer.  Finally, the
display subsystem reads the frame buffer and displays the image on the color monitor.


3.1 Technology Advancements
 

Architecture

Parallelism is exploited extensively throughout the PowerVision graphics
architecture.  The Single Instruction, Multiple Data (SIMD) organization of the
geometric subsystem allows up to tour primitives to be processed in each of two
pipeline elements.  The Multiple Instruction, Multiple Data (MIMD) organization of
the scan conversion and raster subsystem allows up to 200 million pixels to be
processed per second.

Proprietary Graphics Processors

Nine new Custom VLSI processors, implemented in 1.0 micron CMOS, enable
PowerVision systems to realize new levels of performance and functionality.

Floating Point

New, high-speed, floating point data path ASICs in the geometric and scan conversion
subsystems accelerate parallel calculations in PowerVision graphics supercomputers.


3.1.1 VRAM
 

The PowverVision graphics subsystem uses one-megabit video random access memory
(VRAMS) to construct a high-resolution frame buffer with either 140 or 268 bits per