system calls mean the operating system can provide scheduling algorithms that
support, rather than disrupt, the power of private caches.
 
2.2.3 The MPlink Bus
 
The MPlink Bus is a pipelined, block transfer bus that supports the cache consistency
protocol as well as providing 64 megabytes of sustained data bandwidth between the
processors, memory, I/O svstem, and the graphics subsystem.  Because the Sync Bus
provides for efficient synchronization between processors, the cache consistency
protocol is designed to support efficient data sharing between processors.  If a cache
consistency protocol had to support synchronization as well as sharing, it would be
necessary to compromise the efficiency of the data sharing protocol in order to
improve the efficiency of the synchronization operations.  With separate buses for each
of these separate functions, each bus can be designed for optimal performance
without compromise.

The cache consistency protocol is sometimes called the Illinois protocol.  Each second-
level data cache maintains the state values for each cache line.  A line can be in one of
four states: invalid, private read, shared read, or private write.  If a processor writes
into a shared read line, it must invalidate other copies of that cache line before the
write can be completed.  Simultaneous writes into a shared read line by several
processors will result in write misses in all the processors except the one that
successfully acquires the MPlink Bus and Issues an invalidate operation on it.  In
addition, any synchronization operation performed by a processor on the Sync Bus
must not complete until all pending write activity by that processor is complete.

With these simple rules, enforced by the hardware protocols of the Sync Bus and the
MPlink Bus, efficient synchronization and data sharing can be achieved with a simple
shared memory model of parallel processing.  Only the data in another processor's
registers is not visible to a processor.  This invisible data is handled by the Usual
safeguards in modern optimizing compilers.

The physical structure of the MPlink Bus is 32 address lines and 64 data lines.  An
MPlink Bus transaction is six cycles in length, although the last two data transfer
cycles can overlap with the first two cycles of the next transaction, resulting in a
sustainable data transfer rate of 64 megabytes per second in a very economical
configuration.  New data arrives in the last two cycles; old data from a swapped cache
line is carried in the middle two cycles; addresses are transferred in the first two
cycles.  Bus arbitration is pipelined and does not add to the cycle cost of transactions.
 

2.2.4 I/O Bus
 
The POWERpath(tm) architecture also incorporates three separate I/O buses: VME,
Ethernet, and SCSI (Small Computer System Interface).  These buses operate
independently to maximize the I/O throughput of the total system.  The VME bus is
supported by a proprietary SGI chip (DMAP) as a full-functioning, full-performance
VME interfaces VME support includes double- and triple-high EUROcard formats as
bus masters and block mode transfer.

The SCSI bus provides a low-cost, standard interface for disk and tape.  The built-in
Ethernet provides access to TCP/IP and DECnet(tm) networks.