Silicon Graphics' own graphics technology was used in designing the four new CPU
system cards. This allowed two processors to be placed on one card, lowering cost
and size requirements.
2.2 CPU Subsystem Hardware
The fundamental design is tightly-coupled, symmetric, shared memory,2.2.1 Processor Bus
multiprocessing architecture. The CPUs in the POWER Series systems are the MIPS
designed RISC processor, the R3000, coupled with a companion R3010 floating point
Figure 1 shows several of the important buses of the system. The Sync Bus provides
high-speed synchronization between the main processors of the system in support of
fine-grain parallelism. The processor bus allows full-speed access (zero wait-state) to
instructions and data from the individual first-level caches of the main processors.
The read and write buffers allow for the efficient flow of information between the
processors and the main memory of the system. The second-level data cache provides
the additional bandwidth needed with such high-speed processors to support an
automatically consistent shared memory computing model. The MPlink Bus supports
protocols for consistent data sharing and high-speed block data transfers among the
processors, main memory, the I/O system, and the graphics subsystem.
Each processor provides both an address and a data bus (known as the Processor Bus)
that can support sustained data transfers at eight bytes every clock cycle. Thus, an
eight-processor system has a total processor-to-cache bandwidth of 2100 megabytes