1600x1200 pixels at 60Hz non-interlaced. For systems without a second RM board, the
maximum resolution is the standard high-resolution 1280x1024 pixels at the new,
higher-performance, 72Hz non-interlaced refresh rate. This flexibility is supported by
the standard system monitor, a high-resolution multisync display capable of
displaying any video signal up to the new ultra-hi resolution (1600 x 1200) rate.
In addition to the standard video generation capabilities, a special feature has been
added to enable the output of composite video from the standard system. Using a
built-in BNC connector, composite video devices (such as VCRs) may be connected
directly to the system. Rather than performing a scan conversion of the entire display,
the built-in composite video encoder supports the real-time output of NTSC, PAL, or
S-Video from a video-sized window that can be roamed around the display to output
any area of interest. The composite output is performed concurrently with the high-
5.6 Graphics Features And Capabilities
The RealityEiigine has been designed from the start to remove the performance5.6.1 Resolution
penalties associated with the use of such advanced features as anti-aliasing and
texture mapping, while adding a wide range of new functionality to the IRIS Graphics
Librarv (GL). The intent of the RealityEngine architecture was to create a balanced
system enabling the broad range of IRIS applications to achieve peak system
performance rather than setting unattainable performance benchmarks.
The predecessor to the RealityEngine, the IRIS 4D/VGXT, was the first graphics5.6.2 Graphics Primitives
architecture to support a range of resolutions out of one system. RealityEngine takes
that flexibility a step further. The base system includes one Raster Manager (RM)
board and supports resolutions of up to 1280 x 1024 pixels. Adding more RM boards
boosts performance (through additional pixel processors) as well as resolution.
Each RM board provides 1.3M pixels, which can be output in any format desired. To
perform multisample anti-aliasing, a second RM board is required for each 1.3M
pixels to be rendered. This second RM board provides sufficient additional memory to
store the sub-samples for each pixel along with the raster processors to perform the
anti-aliasing computations. Anti-aliasing can be performed on a single RM system but
only if the output resolution is limited to 640x5l2.
The general purpose RealityEngine graphics pipeline supports a wide range of
graphic primitives for the construction and rendering of real-time, 3D objects. The
basic primitives are polygons, vectors, and points, which may rendered with color,
transparency, lighting, texture, and surface properties.
Polygons may have up to 256 sides, but optimal system performance is achieved with
three- or four-sided polygons. Triangles are the basic polygonal building blocks.
When polygons with greater than three vertices are received, they are decomposed
into sets of triangles. For complex, contiguous surfaces, such as terrain in a visual
simulation, polygons may be meshed into short strips with common vertices, which
reduces the demands on the svstem for transformation and makes best use of the