The POWER Series provides a level of processing capability never before achieved in2.1 Technology Advancements
a graphics supercomputer. Combining an advanced CPU subsystem with either
Silicon Graphics VGX/VGXT or industry-leading RealityEngine graphics
architectures, the POWER Series provides the power required by today's most
demanding users. Specifically, the 4D/480VGX system delivers over 286 MIPS, over
70 MFLOPS, 1,000,000 Z-buffered, 3-sided, Gouraud shaded, Phong lighted polygons
per second, and a frame buffer access rate of 20 million pixels per second. This new
level of processing power is made possible by five proprietary VLSI part designs in
the CPU and nine in the graphics subsystem.
The sheer speed of Silicon Graphics' architectures demands high-performance
processing over a high-bandwidth bus. A 3D graphics user requires more memory,
more processing, and more I/O throughput than previously available. It was vital for
Silicon Graphics to enhance the computation portion of the system significantly. The
result is the POWERpath(tm) multiprocessing architecture, a high-power system
designed for the most demanding user.
2.1.1 POWERpath Architecture
Coupling the world's fastest RISC microprocessors with Silicon Graphics' proprietary
chips ind custom system architecture leads to a high-efficiency, high-throughput
system. The goal of the architecture is to maximize the resources available to the user
as needed. Using dedicated subsystems and buses for specific tasks (I/O, memory,
graphics, and so on) avoids penalizing other functions of the system when using the
full performance of any subsystem.
2.1.2 Proprietary Processors
Five new, proprietary VLSI parts in the CPU subsystem and ten proprietary parts in
the graphics subsystem made this new architecture possible and led to reduced cost
with increased reliability and manufacturability.
The latest RAM technology is used to provide zero wait-state access and large cache2.1.4 ECC Memory
sizes for maximum cache hit rates.
A new, proprietary ECC chip provides "blow by" error detection for the memory
subsystem. This ailows the added ECC feature with no memory speed penalty or
extra system cost.