In display list mode, the CPU subsystem feeds the display list to the graphics
subsystem.  When the graphics FIFO buffers are full, the graphics subsystem sends an
interrupt to the CPU to have it wait until the buffers are clear before it sends more
data.

Extensive use is made of custom VLSI ASICs for maximum performance and
capability within the pipeline.  Depending upon the number of Raster Manager (RM)
boards, there can be up to 180 custom processors in the pipeline.  Most of these
processors run in parallel using a MIMD model.  Nine unique ASIC designs are used
in the various stages of the pipeline.


5.3 Geometry Subsystem
 

The first stage of the pipeline is the Geometry Subsystem, which resides on the
Geometry Engine (GE) board.  The two parts of this stage handle the transfer of data
from the bus to the pipeline and the processing of the geometric data as it enters the
pipeline.  At each stage of the pipeline, optimum performance depends upon
maximum utilization of available processing power with as little waiting as possible.
Extensive use of FIFOs insures that no stage of the pipeline keeps any other stage
waiting.


5.3.1 Geometry Engines
 

The Geometry Engines (GE) themselves are standard, off-the-shelf RISC, micro-
processors.  The Geometry Engine architecture uses eight 50MHz Intel i860XP
processors, operating in parallel to magnify the ability of the pipeline to transform
and process geometric data rapidly.  This data is processed bv maintaining a
transformation stack, which performs all the scaling, translating, rotating, and
lighting of polygon, vector, and point vertices.

Each Geometry Engine has its own 2MB DRAM data buffer and a custom buffer
management processor to handle the input queuing of its data stream.  The type of
data passed to the GE is typically vertex data with a large number of parameters
defining the location, orientation, color, and texture mapping coordinates.