maintaining frictional X and Y position information for all primitives enables correct
multipass jittering operations.

The first processor, the Vertex Reorganizer, arranges the stream of commands and
floating point data from the Geometry Engine into points, line segments, triangles, or
quadrilaterals, depending on the command type.  It sends from one to four primitives
to the next stage, the Poly Engine.  In the case of meshes, the VR can distribute up to
four triangles to the four Poly Engine modules.  It also sorts triangle and quadrilateral
vertices by X coordinate to facilitate later computations.

The Poly Engine is a four-module SIMD floating point processor that is nearly
identical in structure to the Geometry Engine.  The Poly Engine begins the scan
conversion process by calculating a number of parameters pertaining to the triangle,
such as the edge and parameter values at the leftmost pixel sample covered, and the
parameter slopes in the X and Y directions.  Cohen-Sutherland clipping, when actually
required, is also performed in the Poly Engine.

The Area Engine is a set of four fixed point processor modules under control of a
single microprogranimed sequencer.  The Area Engine processes floating point initial
value and slope information to produce X, Y, and parameter values for individual
spans of pixels that lie between the top and bottom edges of a triangle.  For each X
coordinate covered by the triangle, it iterates the pertinent two edges and produces
new Y intercepts and exact parameter values along one of the edges.  It passes this
information along with the Y-direction slopes to the Span Processors.

Intercepts and parameter slopes are received by one of five or ten Span Processors (ten
if the MultiBuffer option, a secondary Raster Board, is installed).  In the basic five-span
configuration, each processor handles one-fifth of the 1280 visible screen columns.
Span processor 0 manages columns 0, 5, 10, and so on; span processor I manages
collumns 1, 6, 11, and so on.  Since spans generated from a single polygon are always
adjacent, the span processing load is distributed evenly across the five processors.
Ten-span systems distribute the load similarly with each span handling every 10th
iteration of pixels.

Each Span Processor iterates from the given starting Y address to the ending Y
address, using the slope data to generate Z, color, and texture values in the given
columns These values are passed to the Raster Subsystem to be used update the
display.
 

3.1.6 Raster Subsystem
 
This subsystem contains 20 or 40 Image Engines (IE), each of which is a custom ASIC
that controls a portion of the screen in a two-dimensionally interleaved fashion.  In
the 20-IE configuration, a single IE owns 65,536 screen pixels, each composed of at
least 140 bits of data.  Storing this data requires approximately 23 million bytes of
frame buffer memory (140 bits per pixel for 1.3 million pixels).  The basic organization
of each pixel's 140 bits is in four banks as described below.  When the optional
MultiBuffer raster board is added, an additional 128 bits per pixel provide more
texture memory or hardware acceleration of the SharpScene(tm) Accumulation Buffer
for real-time special effects such as motion blur and full-scene anti-aliasing.