Difference between revisions of "XIO"

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== What is XIO? ==
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XIO is a high-speed communications channel, used for most newer SGI systems ([[IP27]], [[IP30]], [[Origin300|IP35]] - note the [[IP32|O2]] is NOT a XIO system). It's typically used in a switched star topology, the switch being called [[XBow]].
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XIO devices are called [[widget|widgets]].
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'''XIO''' is a packet-based, high-performance computer bus employed by [[SGI Octane]], [[SGI Origin|Origin]], [[SGI Altix|Altix]], [[SGI Fuel|Fuel]] and [[SGI Tezro|Tezro]] machines. It forms a bus between high-performance system devices and the memory controller. XIO devices are called "widgets".
 
'''XIO''' is a packet-based, high-performance computer bus employed by [[SGI Octane]], [[SGI Origin|Origin]], [[SGI Altix|Altix]], [[SGI Fuel|Fuel]] and [[SGI Tezro|Tezro]] machines. It forms a bus between high-performance system devices and the memory controller. XIO devices are called "widgets".
  
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XIO boards use very fragile compression connectors, which should be handled with extreme care.
 
XIO boards use very fragile compression connectors, which should be handled with extreme care.
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== Physical layer ==
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XIO is usually used on a single-ended, source-synchronous physical layer (STL levels - SGI Transistor Logic). It's either an 8- or 16-bit channel, running at 400 MHz (using the dreaded compression connectors). There is also a version, called Crosstown, that uses normal cabling and differential PECL transmission.
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== Link layer ==
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XIO contains a link-layer protocol (LLP) shared with [[CrayLink]]. Transfer is organized into micropackets. These contain a total of 128 bits of data and 32 bits of control. The control information encapsulates an 8 bit sideband (used by higher layers for framing), sequence numbers (for go-back-n link-layer retransmissions) and check bits ([http://en.wikipedia.org/wiki/Cyclic_redundancy_check CRC-16]).
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The link layer is able to run both on 8- and 16-bit links, and if a upper half of a 16-bit link is non-functional, it will automatically revert to using the 8 lower bits.
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== Transactions ==
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XIO supports basic read/write memory transactions. IRQs are sent through XIO by instructing a device to write a defined value to some register in another XIO widget. This write actually triggers the IRQ handling process in the interrupt controller. For instance, the [[SGI_Octane#HEART|HEART]] chip has such register at 0x80 in XIO widget space.
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XIO addresses differ from physical processor addresses. They are two-part (widget-offset) and each XIO device is free to implement the translation from its unified memory space to the XIO address. [[BRIDGE]] and [[SGI_Octane#HEART|HEART]] are examples of two different approaches.
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== Device identification ==
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There is no distinction between memory and configuration space in XIO. Instead, each XIO device has a predefined header that consists of a [[widget|widget ID]] and several configuration registers.
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[[Category:SGI]]
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[[Category:Computer buses]]
 
[[Category:Computer buses]]
 
[[Category:HowTo]]
 
[[Category:HowTo]]
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[[Category:Hardware]]

Latest revision as of 16:27, 25 December 2010

What is XIO?

XIO is a high-speed communications channel, used for most newer SGI systems (IP27, IP30, IP35 - note the O2 is NOT a XIO system). It's typically used in a switched star topology, the switch being called XBow.

XIO devices are called widgets.


XIO is a packet-based, high-performance computer bus employed by SGI Octane, Origin, Altix, Fuel and Tezro machines. It forms a bus between high-performance system devices and the memory controller. XIO devices are called "widgets".

XIO is usually used in a star topology -- a router called Xbow (cross-bow) connects up to eight fully-symmetrical devices in a system (typically, one of them is the memory controller / CPU bridge, called HEART in Octane or HUB in Origin).

Other devices known to have XIO interfaces are:

  • BRIDGE: XIO to PCI-64 bridge (Octane, Origin)
  • XBRIDGE: XIO to PCI-X bridge (Altix)
  • HQ4: command processor of ImpactSR cards (Octane)
  • KTOWN: frontend for InfiniteReality2 cards (Onyx, Origin variation)
  • XC: Crosstown converter


XIO employs two source-synchronous channels (one in each direction), each 8 or 16 bits wide. They are clocked at 400 MHz to achieve peak rates of 800 MB/s. Each of the devices can utilize the full bandwidth, as the XBow router prevents collisions by being able to route between any two points.

Transfer is organized into micropackets. These contain a total of 128 bits of data and 32 bits of control. The control information encapsulates an 8 bit sideband (used by higher layers for framing), sequence numbers (for go-back-n link-layer retransmissions) and check bits (CRC-16). The link layer is able to run both on 8- and 16-bit links, and if a upper half of a 16-bit link is non-functional, it will automatically revert to using the 8 lower bits.

XIO is usually used on a single-ended, source-synchronous physical layer (STL levels - SGI Transistor Logic). There is also a version called Crosstown, which uses normal cabling and differential Positive Referenced Emitter Coupled Logic (PECL) transmission.

XIO boards use very fragile compression connectors, which should be handled with extreme care.




Physical layer

XIO is usually used on a single-ended, source-synchronous physical layer (STL levels - SGI Transistor Logic). It's either an 8- or 16-bit channel, running at 400 MHz (using the dreaded compression connectors). There is also a version, called Crosstown, that uses normal cabling and differential PECL transmission.

Link layer

XIO contains a link-layer protocol (LLP) shared with CrayLink. Transfer is organized into micropackets. These contain a total of 128 bits of data and 32 bits of control. The control information encapsulates an 8 bit sideband (used by higher layers for framing), sequence numbers (for go-back-n link-layer retransmissions) and check bits (CRC-16).

The link layer is able to run both on 8- and 16-bit links, and if a upper half of a 16-bit link is non-functional, it will automatically revert to using the 8 lower bits.

Transactions

XIO supports basic read/write memory transactions. IRQs are sent through XIO by instructing a device to write a defined value to some register in another XIO widget. This write actually triggers the IRQ handling process in the interrupt controller. For instance, the HEART chip has such register at 0x80 in XIO widget space.

XIO addresses differ from physical processor addresses. They are two-part (widget-offset) and each XIO device is free to implement the translation from its unified memory space to the XIO address. BRIDGE and HEART are examples of two different approaches.

Device identification

There is no distinction between memory and configuration space in XIO. Instead, each XIO device has a predefined header that consists of a widget ID and several configuration registers.