Difference between revisions of "R6000"

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The '''R6000''' is a microprocessor chip set developed by [[MIPS Computer Systems]] that implemented the [[MIPS II]] [instruction set architecture (ISA). The chip set consisted of the R6000 microprocessor, R6010 floating-point unit and R6020 system bus controller. The R6000 was the first implementation of the MIPS II ISA.
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The R6000 was implemented with emitter-coupled logic (ECL). In the mid- to late 1980s, the trend was to implement high-end microprocessors with high-speed logic such as ECL. As MIPS was a fabless company, the R6000 chip set was fabricated by Bipolar Integrated Technology.
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The R6000 had few users. Control Data Systems (CDS) used an 80 MHz version in their high-end 4680-300 Series InforServer server. MIPS used the R6000 in their RC6260 and RC6280 servers.
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==References==
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* "MIPS Chip Set Implements Full ECL CPU". (December 1989). ''Microprocessor Report''. pp. 1, 14–19.
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* Horowitz, M. et al. (1990). [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=110133 "A 3.5ns, 1 Watt, ECL register file"]. ''ISSCC Digest of Technical Papers'', pp. 68–59, 267.
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* Roberts, D.; Layman, T.; Taylor, G. (1990). [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=63680 "An ECL RISC microprocessor designed for two level cache"]. ''Compcon Spring '90 Digest of Technical Papers'', pp. 228–231.
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<!--* Taylor, G. et al. (1990). "An 85 MHz ECL RISC processor with on-chip address translation and two-level cache control". ''ISSCC Digest of Technical Papers'', pp. 40&ndash;41..-->
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* Thorson, M. (January 1990). "ECL Bus Controller Hits 266 Mbytes/s". ''Microprocessor Report''. pp. 12&ndash;13.
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[[Category:Microprocessors]]
 
[[Category:Microprocessors]]

Latest revision as of 11:14, 11 October 2011

The R6000 is a microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS II [instruction set architecture (ISA). The chip set consisted of the R6000 microprocessor, R6010 floating-point unit and R6020 system bus controller. The R6000 was the first implementation of the MIPS II ISA.

The R6000 was implemented with emitter-coupled logic (ECL). In the mid- to late 1980s, the trend was to implement high-end microprocessors with high-speed logic such as ECL. As MIPS was a fabless company, the R6000 chip set was fabricated by Bipolar Integrated Technology.

The R6000 had few users. Control Data Systems (CDS) used an 80 MHz version in their high-end 4680-300 Series InforServer server. MIPS used the R6000 in their RC6260 and RC6280 servers.

References

  • "MIPS Chip Set Implements Full ECL CPU". (December 1989). Microprocessor Report. pp. 1, 14–19.
  • Horowitz, M. et al. (1990). "A 3.5ns, 1 Watt, ECL register file". ISSCC Digest of Technical Papers, pp. 68–59, 267.
  • Roberts, D.; Layman, T.; Taylor, G. (1990). "An ECL RISC microprocessor designed for two level cache". Compcon Spring '90 Digest of Technical Papers, pp. 228–231.
  • Thorson, M. (January 1990). "ECL Bus Controller Hits 266 Mbytes/s". Microprocessor Report. pp. 12–13.